Electrostatic discharge (ESD) protection is a great concern in low voltage deep-submicrometer silicon technology. The reliability of silicon integrated circuits (ICs), due to smaller feature sizes, is becoming more and more critical. With thinner gate oxide thickness, silicon circuits are more sensitive to the stress from ESD. During manufacture and assembly of ICs ESD may cause damage. Despite the mature technology of high speed switching, and high-voltage robustness for DC ESD protection, radio frequency (RF) ESD protection design in state-of-the-art silicon technologies is still a challenge—especially or high voltage applications.
More specifically, RF power amplifiers require large signal swings both above and below ground, and they need to operate at a high frequency. This becomes particularly challenging in the case where the voltage swing at a pad node of an integrated circuit, coupled to a PA, exceeds the operating limits of the available silicon process.
FIG. 1 depicts a typical schematic block diagram representing ESD protection circuit 102 of integrated circuit (IC). The representation illustratively depicts ESD protection circuit 102, coupled at one end to a protected node of IC 100 and IC pad 104, and at the other end to ground. ESD protection circuit 102 comprises an ESD protection device such as a cascode grounded gate snap-back NFET (GGNFET). ESD protection circuit 102 comprises two NFET devices, Np1 and Np2, in a cascode configuration.
Under normal operation of IC 100 ESD protection circuit 102 should be off. During a positive polarity ESD pulse, the GGNFET provides an active discharge path to shunt a current surge from IC pad 104 to ground. Furthermore, it clamps the IC pad voltage to a sufficiently low level to avoid damaging the protected circuit node of the IC.
ESD protection circuit 102 is characterized by a turn-on voltage. This is the maximum voltage the ESD protection circuit can withstand before it turns on. More specifically ESD protection circuit 102 can withstand, during normal operation, two times the maximum operating voltage of each NFET. As an example, in a typical 65 nm process long channel NFETs have a maximum operating voltage of 3.6 Volts, therefore the maximum allowable voltage swing at the IC pad is 7.2V. Integrated silicon PA output voltage swing requirements may exceed the 7.2 volts, making the ESD protection circuit shown in FIG. 1 a poor choice for PA designs requiring voltage swings above 7.2V.
Furthermore, the GGNFET requires drain ballast resistance to achieve conduction uniformity. The ballasting requirement greatly increases the parasitic load capacitance at the drain node D of the GGNFET, thus limiting the high frequency operation of the RF power amplifier. As the operating frequency increases to the gigahertz range, the parasitic capacitance acts as a low impedance path to ground and significantly degrades the performance of the RF Power Amplifier, or any other RF circuit coupled to the IC pad.
For radio frequency integrated circuits (RFICs), it is imperative to develop ESD protection circuits with low parasitic capacitance for high voltage, high frequency applications.